at the same time, if you're transpiling from something else, verilog is MUCH better than VHDL because as a language it has a much smaller surface area.
Modulo "HDL is different because everything is synchronous" and the testing DSL, You can learn most of verilog in a day, not so much VHDL.
Modulo "HDL is different because everything is synchronous" and the testing DSL, You can learn most of verilog in a day, not so much VHDL.