On: Verilog Simulation with Verilator and SDL

[Arch-TK]

I imagine you think pascal and ada have horrible syntax too?

For me, the syntax is ideal. On the plus side VHDL seems to have actually been designed with the intention of being used for FPGA designs. Verilog on the other hand just seems like a hack in comparison.

[leche → Arch-TK]

The opposite is true. VHDL was originally designed as an implementation-agnostic documentation and description language.