It'd assume its just "asymmetric SMT" as a model. Each "hardware core" is seen as 2x big hardware thread + 1x small hardware thread.
The 2x big hardware threads are from the big-core (SMT / Hyperthreading), while the 1x small hardware thread is the small-core.
Since this chip is 8-big cores + 8 little cores, the math works out.
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A future chip is rumored to be 8-big cores + 16 little cores, which can be implemented instead as 2x big-threads + 2x little-thread cluster (1x big core + 2 little cores per cluster).
Though of course, that depends heavily upon the implementation details of this "Thread Director".
The 2x big hardware threads are from the big-core (SMT / Hyperthreading), while the 1x small hardware thread is the small-core.
Since this chip is 8-big cores + 8 little cores, the math works out.
-----
A future chip is rumored to be 8-big cores + 16 little cores, which can be implemented instead as 2x big-threads + 2x little-thread cluster (1x big core + 2 little cores per cluster).
Though of course, that depends heavily upon the implementation details of this "Thread Director".