> If you design a CPU capable of holding many threads context within silicon (on die memory) you might get closer to a GPU.
From a pure programming model POV, this is just SMT which RISC-V supports quite handily - the native "core"-like abstraction is specifically pointed out as a 'hardware thread', "hart" for short. Now, clearly GPGPU adds some features that are not encompassed by this model, such as vartious sorts of "scratchpads"/"memories" often with restricted addressing. But the general feature is accounted for.
From a pure programming model POV, this is just SMT which RISC-V supports quite handily - the native "core"-like abstraction is specifically pointed out as a 'hardware thread', "hart" for short. Now, clearly GPGPU adds some features that are not encompassed by this model, such as vartious sorts of "scratchpads"/"memories" often with restricted addressing. But the general feature is accounted for.