Apple is probably paying closer to $20k per wafer, including test and packaging. There have been leaks on pricing in the industry, leading edge process is expensive. Even at 50M chips. TSMC is in a position to command a price that pays to build the next gen fab, and there are other customers.
Masks are also a significant expense. N5 is an EUV intensive process with $10..20M per set. They probably run through a new mask set every 50,000 wafers or so, and likely need 2 mask sets to get beyond 10,000 (two days) so they can swap them out for inspection and cleaning. So their mask costs for the 100,000 wafers they need are somewhere above $50M.
It is interesting to compare with a project like Graviton2 on N7, which is more like $12k per wafer including test and packaging and likely 120 chips yielded at 4cm2 each. They probably need 2M chips per generation, and as their design is not nearly as aggressive as the A14, with far fewer different functional blocks and mostly off the shelf IP, they may have done it with as little as $200M of R&D. So they can get a G2 for as low as $200, maybe as much as $300. That makes each core $5 or less. About a third the price of the DRAM they need per core.
From my experience in budgeting, the cost of an employee for this kind of technical enterprise is about double their salary. That includes employment taxes, benefits, and employee-specific overhead (laptops, office space, licenses, etc.).
Salary != fully loaded cost to the company. Just the company paid portion of income taxes can add another 15% alone easily. Then you have health insurance, office space, perks, etc and you can easily get in the range of 1.5 - 2x the salary.
Does that mean they don’t exist? Are the FAANG chip makers paying a lot more for engineering than in the asics space? Genuine questions, I have a growing interest in this (vast) space.
Definitely more than Apple and Intel, Google hires and pays for superior intellect. Only place that might pay better is specialized telco hardware engineers in finance (but that’s not of the same magnitude as modems or TPUs)
It might be interesting to compare with the math for some of the earlier working bitcoin ASIC miner chips. Those are obviously much, much, simpler, but could represent a realistic low end.
Masks are also a significant expense. N5 is an EUV intensive process with $10..20M per set. They probably run through a new mask set every 50,000 wafers or so, and likely need 2 mask sets to get beyond 10,000 (two days) so they can swap them out for inspection and cleaning. So their mask costs for the 100,000 wafers they need are somewhere above $50M.
It is interesting to compare with a project like Graviton2 on N7, which is more like $12k per wafer including test and packaging and likely 120 chips yielded at 4cm2 each. They probably need 2M chips per generation, and as their design is not nearly as aggressive as the A14, with far fewer different functional blocks and mostly off the shelf IP, they may have done it with as little as $200M of R&D. So they can get a G2 for as low as $200, maybe as much as $300. That makes each core $5 or less. About a third the price of the DRAM they need per core.