> Some chips get downgraded in the process: if you can't sell a 4-core CPU with 8MB of L1 cache, you can disable the core that fails tests, and / or disable the parts of the cache that fail tests, and sell a 3-core part with 4MB cache; AMD did just that back in the day.
How does that work anyway? I mean, how is a processor actually tested at the pre-packaging stage, given that you'd need to provide it with power and cooling for a test?
They use a wafer tester that literally has a tiny bed-of-nails array on it that contacts the bumps for a given die on the wafer, and can move over the wafer in x and y. It provides power and test signals, although power is typically quite limited (<100A of current or so). The good die will then go on to get packaged and further tested before being assembled onto a PCB
I'd assume they attach it to the substrate, glue on the IHS (the lid), and run diagnostics on the completed chip. If any issues are detected, the processor would contain functions to disable certain blocks (through JTAG or something).
How does that work anyway? I mean, how is a processor actually tested at the pre-packaging stage, given that you'd need to provide it with power and cooling for a test?