It's not just the small volume. Having worked on a number of ASIC + eval-board combos, there are several issues:
1) Eval board design typically begins before the ASIC design is finished. This means eval boards are frequently subject to last-minute design changes (because something in the ASIC changed) and/or intense schedule pressure for the design to be completed and the boards manufactured between the ASIC design freeze and when the ASIC comes back from the fab. Last minute design changes and high schedule pressure are not conducive to high-quality engineering.
2) Eval boards frequently have multiple purposes. The primary focus of an "eval" board is likely to be test platform for the ASIC, and customer evaluation is a secondary goal at best. As an external customer of the eval board, you're not even the _primary_ customer - the primary customer is the internal testing team. If "easy for the test team to use" and "easy for an outside customer to use" ever come into conflict, the test team is going to win.
2b) Because eval board's real target customer is a team within the company that has access to the ASIC documentation, preparing external documentation is a low priority. And since eval boards can indirectly expose embarrasing bugs in the ASIC, design secrets, etc., the external documentation is either heavily redacted, gated by onerous NDAs, or both.
3) Eval boards aren't the product - the product is the ASIC - and selling eval boards is rarely profitable on net, so there's pressure to keep the costs down. In the same vein, the PCB team for a semiconductor company is considered lower status within the ASIC company (if they're even part of the company and not contractors or an outside design house, which is also very common). This doesn't mean they're less skilled, necessarily, but it does mean they have fewer resources and less influence within the company, so "eval board" issues are going to be low priority.
3b) Because eval boards are a net loss, the incentive to go back and clean up any issues caused (1) and (2) is low to non-existent.
4) Because the eval boards _never_ go to high volume production, the eval board design team frequently has no experience or motivation to do proper DFM (design for manufacturing) or DFT (design for test) on their PCBs. Assembly is frequently manual because the volumes are too low to justify setting up (and debugging) an automated assembly line, leading to high product variability.
5) The eval board price is intentionally high to filter out non-serious users who're not engineering with a plan for eventual high volume production. Sales reps may just eat the cost of some dev resources if it enables a volume sale, or get it reimbursed as promotional expenses.
I met with a field engineer for a major chipmaker. I asked him about the samples that he tossed to our group, he said he usually just got them from DigiKey.
> The eval board price is intentionally high to filter out non-serious users who're not engineering with a plan for eventual high volume production.
+1. Also, they know you cannot do your job without them, and anyone who's buying one is a company with a budget, thus, it allows them to set the price to the maximum that is still accepted by companies. It's not unusual to sell a $200 eval board for a $2 commodity chip. Fortunately, at least for cheap commodity chips, the reference schematics and layout is often available for free.
1) Eval board design typically begins before the ASIC design is finished. This means eval boards are frequently subject to last-minute design changes (because something in the ASIC changed) and/or intense schedule pressure for the design to be completed and the boards manufactured between the ASIC design freeze and when the ASIC comes back from the fab. Last minute design changes and high schedule pressure are not conducive to high-quality engineering.
2) Eval boards frequently have multiple purposes. The primary focus of an "eval" board is likely to be test platform for the ASIC, and customer evaluation is a secondary goal at best. As an external customer of the eval board, you're not even the _primary_ customer - the primary customer is the internal testing team. If "easy for the test team to use" and "easy for an outside customer to use" ever come into conflict, the test team is going to win.
2b) Because eval board's real target customer is a team within the company that has access to the ASIC documentation, preparing external documentation is a low priority. And since eval boards can indirectly expose embarrasing bugs in the ASIC, design secrets, etc., the external documentation is either heavily redacted, gated by onerous NDAs, or both.
3) Eval boards aren't the product - the product is the ASIC - and selling eval boards is rarely profitable on net, so there's pressure to keep the costs down. In the same vein, the PCB team for a semiconductor company is considered lower status within the ASIC company (if they're even part of the company and not contractors or an outside design house, which is also very common). This doesn't mean they're less skilled, necessarily, but it does mean they have fewer resources and less influence within the company, so "eval board" issues are going to be low priority.
3b) Because eval boards are a net loss, the incentive to go back and clean up any issues caused (1) and (2) is low to non-existent.
4) Because the eval boards _never_ go to high volume production, the eval board design team frequently has no experience or motivation to do proper DFM (design for manufacturing) or DFT (design for test) on their PCBs. Assembly is frequently manual because the volumes are too low to justify setting up (and debugging) an automated assembly line, leading to high product variability.