If you really wanted to support any denominator for a 16-bit division in a space efficient way, it seems like you could just subtract the denominator from the numerator in a loop, counting iterations until it's less than the denominator. I can't imagine it's more than a dozen assembly instructions, even on a crappy architecture. Worst case (divide by 2), it takes 32767 iterations, and you even get the remainder out of it.
With this example, say 100C. Convert to deciC and offset, say, 25 degrees to make it unsigned. 1250. Multiply by 9. 11250. Divide by 5 takes 2250 iterations. I am unfamiliar with the MCS-48, but Google says it can be clocked at 11Mhz. It would take maybe 40ms to do the divide?
With this example, say 100C. Convert to deciC and offset, say, 25 degrees to make it unsigned. 1250. Multiply by 9. 11250. Divide by 5 takes 2250 iterations. I am unfamiliar with the MCS-48, but Google says it can be clocked at 11Mhz. It would take maybe 40ms to do the divide?