Kind of off topic, but how much time is involved building processors with FPGA's, especially for modern architectures like RISC-V? I only have a very basic overview knowledge about FPGA's and almost none at the time about HDL's (I plan on learning!), but with the complexity involved in modern processors, I can't imagine this being a few weeks or even months or work.
RISC-V as an ISA is designed to be easy to implement. You can get a simple implementation in 3k lines of Verilog [1].
That being said, there's a huge difference between a toy / simple multi-cycle machine-mode RISC-V core and one with a modern, performent microarchitecture (pipelined, super-scalar, multi-issue, cache coherent across multiple cores, with efficient branch prediction). There's also extra work to implement RISC-V extensions that let you run any 'real' code like Linux (which requires anything from simple ISA extensions to implementing the Privileged Instruction spec which dictates additional things like the MMU and interrupt controller).
It depends what you want to do? Do you want to build a processor from scratch? A basic processor for core RISC-V is actually quite simple. The RISC-V I specification (all the core instructions not including multi/div, none of the privileged spec) is not complex.
Implementing something like the story talks about is obviously far more complex.
If you're mostly interested in putting together existing processors that can again can vary in complexity, there are some things with 'batteries included' where you can just spin up an FPGA image that works then go poking around, others where there will be significant work in integrating things into a working system.
I'll give a plug to Ibex (https://github.com/lowRISC/ibex) which is the core I work on, it doesn't have an MMU and is targetted at embedded applications. It's a 'real' core, in that it's suitable for taping-out into a real system but still quite simple to understand. OpenTitan (https://github.com/lowRISC/opentitan) is a notable project we're also working on that uses it, it's an open source root of trust and will give you a working RISC-V SoC you can put on an FPGA, you can easily carve out the security things leaving you with a RISC-V core, some SRAM and various useful peripherals.
