On: AMD Rome – is it for real? Architecture and initia...

[old-gregg]

The central I/O die does not have any cache on it. L3 caches are shared across just 4 cores in a CCX (not even CCD).

IIRC the next generation of Ryzen will introduce CCD or even I/O die caches. I think one of Intel's Broadwell chips had L4, so it's the same idea.