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toast0
on Oct 23, 2019
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AMD Rome – is it for real? Architecture and initia...
If your stack is NUMA aware, and can manage that 4/8 partitions, enabling it would seem to reduce memory contention between chiplets; even if there isn't a latency penalty for going a bit farther to memory (which there likely is, but probably small)
dragontamer
on Oct 23, 2019
[–]
The STREAM benchmark doesn't have any memory contention at all. Its basically a full tilt "write to memory / read from memory" kind of benchmark.
toast0
on Oct 23, 2019
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I would expect memory
bus
contention in a benchmark like that.
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