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loeg
on Oct 23, 2019
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AMD Rome – is it for real? Architecture and initia...
Perhaps, as article sort of suggests, inside the IO chiplet there are four quadrants that each have two memory controllers associated with them, and the cross-quadrant bandwidth isn't sufficient for 75% non-local memory bandwidth.
wmf
on Oct 23, 2019
[–]
I made a video yesterday with some details on this topic:
https://youtu.be/ghFx_jyP1U8?t=390
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