On: Compiling my own SPARC CPU inside a cheap FPGA

[alain94040]

Great article, I hope it helps motivate more people to give hardware design a try.

the truth is that most of the HW designers I know are editing inside their Vendor-provided IDEs.

Maybe true for FPGA designers, but not for ASIC designers in my experience.

Another crazy difference I experienced was that builds are NOT deterministic

Yes, hardware generation (synthesis, but mostly optimizations, placement and routing) are not deterministic. SW people are starting to experience that phenomenon with ML as well: you don't fully control what you get, but it works.

[bpye → alain94040]

With HW generation given the same HDL and tools you should be able to get reproducible builds if you provide the same seed at the very least.

[tverbeure → bpye]

In theory, you should. In practice, don't count on it.