On: Compiling my own SPARC CPU inside a cheap FPGA

[tverbeure]

I stand corrected!

I really should get the DRAM working on the G2. How hard could it be?

[oneplane → tverbeure]

Famous last words. But I do hope you manage to get access to that sweet memory, it would make software life so much easier.

[jacquesm → tverbeure]

A couple of weeks of very hard work at a minimum :) Maybe a year or so on the outside. But please do!

[tverbeure → jacquesm]

How about 9 hours? :-)

Just got it up and running with a 125MHz clock and the Xilinx MIG (memory interface generator.)

[gardintrapp → tverbeure]

Did you connect the the memory controller Xilinx MIG to the AHB interconnect of Leon?

I used a similar DDR2 memory (MT47H64M16 I think) on a Cyclone III a few year ago. Using the ALTMEMPHY from Altera it was not to difficult to make it work. Then later we got a new batch of cards witch would randomly fail. The problem was that DDR had been switched from Micron to an equivalent from Samsung. But the timing must have been just different enough to cause random fails. So yes DDR2 memories can be tricky.

Many years ago at University I used Leon and grlib for a project. It was a nice processor and IP library. I would like to use it again.

[jacquesm → tverbeure]

Hah! Awesome.