On: Compiling my own SPARC CPU inside a cheap FPGA

[tpmx]

Any links to reading materials for learning about that?

Found this PDF from Samsung regarding the DDR4 interface itself:

https://www.samsung.com/semiconductor/global.semi/file/resou...

(The JEDEC DDR4 spec is $284 to download...)

[lnsru → tpmx]

Start reading data sheets of memory chips. They have state diagrams. DDR2 is great technology to start with. Some random memory chip: https://www.micron.com/-/media/client/global/documents/produ... on page 9 you have state diagram. There is simulation model available.

[exikyut → lnsru]

Where is this simulation model, and (here's hoping) is it cross-platform?

Also, is it anything like http://www.visual6502.org/JSSim/?

[lnsru → exikyut]

On Micron’s website for most of their parts. Worked very well with Alteras’s memory controller some time ago. I needed to evaluate read write throughput for specific read/write patterns before designing printed circuit boards. I don’t unterstand what you mean with cross-platform.