Yeah - typically print the entire wafer then compare dies within a field (usually there are multiple dies exposed in a single exposure) to see which defects are in the same place on each field. This won’t work if there is only one die per field, as could be the case for an exceptionally large server chip. In that case you probably need to predict what the image will look like based on design files and then compare with the actual image and look for differences. You could also e-beam scan the whole wafer but this can take a while (like 30 days when I was around), night damage the wafer, and bumps up against the reliability of E-beam components. It wasn’t being seriously considered.
