> Well it's solved in that all mem accesses now uniformly are a bit slower as all have to go through the new memory access hub. Is this a correct reading?
Yes. But the new EPYC chips have doubled their L3 cache, and that new memory-access hub has stupidly high bandwidth.
The larger L3 cache mitigates the latency problems, while the memory-access hub has more than enough memory-bandwidth to feed all the cores.
Yes. But the new EPYC chips have doubled their L3 cache, and that new memory-access hub has stupidly high bandwidth.
The larger L3 cache mitigates the latency problems, while the memory-access hub has more than enough memory-bandwidth to feed all the cores.