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I wish they had waited until the riscv-formal work was a little farther on. I have a distinct feeling we're going to uncover some goofiness in the spec from that work.



At some point you have to ship, and thanks to the awesomeness of semantic versioning, they can always release RISC-VI :)

/s


There is no reason "move fast and break things" should not work for hardware too

/S




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