This sounds a lot like the abstraction that SystemVerilog uses to describe the electronic states that a piece of wire can be in. Namely, SystemVerilog uses 0 for a wire driven by a low voltage, 1 for a wire driven by a high voltage, Z (high impedance) for a wire that is not being powered at all, and X (unknown) for a wire that is driven by a 0 and a 1 at the same time.
X is highly contagious, if you connect any wire to one with an X value, the result will be X. On the other hand, Z wires have their value overwritten by anything (a 0 connected to a Z will result in a 0). However, Z is not a valid _input_ to a logic gate: 1 AND Z = X.
Z is usually used for buses which consist of multiple inputs and outputs connected to the same wire. When nobody is transmitting, the value of the bus is Z. When one device transmits, the bus takes the value of the transmission. And finally, if more than one device attempts to transmit at a given time the result is X and you get what is known as bus contention :)
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The abstraction you mentioned isn't really similar to what I mentioned in parent. INVALID would be like X, I guess, but there is no counterpart of Z in the logic I used daily. Nonetheless it's interesting to learn about the abstraction :)
Lots of insanity here too. Like, “~(~(a)) = a” is no longer a correct rule (because when negated twice, z becomes x). But other than that it’s a cool system.
X is highly contagious, if you connect any wire to one with an X value, the result will be X. On the other hand, Z wires have their value overwritten by anything (a 0 connected to a Z will result in a 0). However, Z is not a valid _input_ to a logic gate: 1 AND Z = X.
Z is usually used for buses which consist of multiple inputs and outputs connected to the same wire. When nobody is transmitting, the value of the bus is Z. When one device transmits, the bus takes the value of the transmission. And finally, if more than one device attempts to transmit at a given time the result is X and you get what is known as bus contention :) ~