You'd need to grab the address and data buses, and synchronise that to a point in the fetch cycle when the data is guaranteed to be stable.
It also means a lot more test clips to connect... A 16-bit bus with 16-bit addressing would be 33 data clips and a couple of grounds. In a cardcage type system you'd need an extender card to do this. Without an extender card you need to solder in test pins or wires. Not something I'd want to do to a 40-year-old museum piece.
There's a picture in the repo it looks like he is using a logic analyzer. He also mentions the backplane is wire wrapped, making it easy to connect wires.
They probably could have also used an arduino with some circuitry to automate the stepping and address line management, as well as read the data lines. This assumes of course that the PALM has such systems.
My guess? The writer had OCR on the mind and decided "Why not?"
That must be why John Titor needed to go back to 2000 to retrieve one.