On: Verilator: Fast, Free Verilog HDL Simulator

[Cyph0n]

In my experience, it's:

1) Less verbose and easier to write, but slightly more "error" prone (think: Java vs. Python).

2) More widely used in industry. VHDL is more heavily used in the defense industry (it came out of DoD).

3) Better support for verification (e.g., SystemVerilog).