Compared to other CISC CPUs designed at the same time as x86s (Vax, 68k, 32k, etc) x86s ARE positively RISCy - the instruction set (with 1 or two minor exceptions - push) only has instructions with 1 memory address making exceptions/restart (paging code) simple and making instructions easy to break into simple uOps (one trip to the TLB for protection checking - Vaxes used to potentially do 27 and guaranteeing that instructions could make progress in all situations was problematical)
