I don't know why this gets thrown around but it's completely wrong. RISC and CISC are about instruction set architecture. As soon as you have crossed the decoder boundary you are deep into micro architecture territory where the ISA is completely irrelevant because you can use the same techniques regardless of whether you have RISC or CISC.
Now if one would take what you said at face value then it would actually imply that RISC as an ISA is completely irrelevant because it is possible to achieve the same benefits or even beat it despite CISC having the inefficiency of hard to decode instructions and the high cost of a conversion step in the micro architecture. One suddenly realizes that this battle of ISAs is completely futile and the secret sauce is in the micro architecture which is completely divorced from the ISA.
Here are some examples: ARM makes slow ARM chips. Apple makes fast ARM chips. AMD made slow x86 chips in the past but now adopted a faster micro architecture. Intel made Itanium but the chips didn't have any sort of dynamic scheduling so they couldn't deliver the promised performance gains.
Now if one would take what you said at face value then it would actually imply that RISC as an ISA is completely irrelevant because it is possible to achieve the same benefits or even beat it despite CISC having the inefficiency of hard to decode instructions and the high cost of a conversion step in the micro architecture. One suddenly realizes that this battle of ISAs is completely futile and the secret sauce is in the micro architecture which is completely divorced from the ISA.
Here are some examples: ARM makes slow ARM chips. Apple makes fast ARM chips. AMD made slow x86 chips in the past but now adopted a faster micro architecture. Intel made Itanium but the chips didn't have any sort of dynamic scheduling so they couldn't deliver the promised performance gains.