> I like to think that it is possible we'll one day develop a CPU architecture that is both simple enough to reason about and also highly performant.
RISC-V is getting there, with open-hardware cores such as Rocket (in-order) and BOOM (out-of-order). Too bad that many and perhaps most of the peripheral components even on a general-purpose SiFive SoC are still closed hardware blocks. But people are working on opening these up as well.
RISC-V is getting there, with open-hardware cores such as Rocket (in-order) and BOOM (out-of-order). Too bad that many and perhaps most of the peripheral components even on a general-purpose SiFive SoC are still closed hardware blocks. But people are working on opening these up as well.