The very quick explanation is that when you have lots of long wires (and especially wires of different lengths) between the components of your chip, you have to wait for all the signals on a bus to arrive before you can latch them into the component at the next clock edge, and this slows down the achievable clock speeds.
To explain this properly would require explaining how FPGAs work and how they differ from ASICs. There's a rather good talk by Uli Drepper which covers some FPGA basics: https://www.youtube.com/watch?v=Q-SkioVSZWw
In any case 100 MHz for an FPGA processor design is not slow for an FPGA, nor is it something that can be solved with more money (bigger and smaller FPGAs suffer the same effect). For GHz designs you have to implement an ASIC. For comparison, SiFive's FPGA implementation runs at 100 MHz but their ASIC of near-exactly the same design runs at 1.5 GHz.
