The 8087 FPU was not offloading the CPU as the CPU was halted after the FPU caught a FP instruction and made a DMA call to the CPU and took control of the bus to access what memory it had to. They were a tag-team if you will; jumping in and out of the ring to deal with their respective instructions.
Halted?
You had an option to WAIT for 8087 but you could 'cheat' and just run other instructions, manually calculating cycles.
Thus, a system with an 8087 was capable of true parallel processing, performing one operation in the integer ALU of the main CPU while at the same time performing a floating-point operation in the 8087 coprocessor. Since the 8086 or 8088 exclusively controlled the instruction flow and timing and had no direct access to the internal status of the 8087, and because the 8087 could execute only one instruction at a time, programs for the combined 8086/8087 or 8088/8087 system had to ensure that the 8087 had time to complete the last instruction issued to it before it was issued another one.
I believe Agnus(?) and the CPU had to wait on each other for the memory bus - as evidenced by the CPU getting slower when the screen resolution was increased, due to the greater amount of video memory being read per frame.
