Serious question: what is an AI coprocessor technically? Some machine learnt models burned on a chip? Or some kind of a neural net with updatable weights?
There are many potential designs for these things, but the first gen TPU is one that works, is in production, and has been described in a paper. But you have to differentiate if you mean an inference engine, or something that can also do training. For HoloLens, it's probably going to be an inference unit, which means it'll possibly look something like a TPU, perhaps with more specific hardware support optimized for convolutions (which are very important for visual processing DNNs these days), as the NVidia tensor units are.
It is not well documented by anyone. However, the expectation is that it is a matrix or convolution coprocessor, as this is a common operation in deep neural networks (for both inference and training). For instance, NVIDIA says they are supporting 4x4 convolutions with the tensor unit.
I was in the audience at CVPR when it was presented. They were doing semantic segmentation using resnet-18, so I'm guessing it speeds up convolutions and some linear algebra during inference. I'm guessing it won't be used for training.
According to the linked article, this coprocessor seems particularly focused on Deep Neural Networks (DNN), so it does sound like a updatable weight neural network evaluator.
