Those limitations sounds awfully similar to that of an FPGA.. | Hacker News

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pavanky on April 5, 2017 | parent | context | favorite | on: An In-Depth Look at Google's Tensor Processing Uni...

Those limitations sounds awfully similar to that of an FPGA..

vvanders on April 5, 2017 [–]

I was going to say as well. It seems like if caches are the bane of sequential processing(CPU) then routing has to be the counterpart on the parallel(FPGA/ASIC) side of the equation.

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