Hey, chipmakers deserve more credit than that! I'm a chip architect and we license from IMG and we license IP from others as well, but then there's a shitton of work and plenty of things which can go wrong, costing loads of money and big delays. For those chip makers rolling their own IPs, this is rarely the biggest risk, the biggest risk is integrating everything into a working, marketable chip delivered more or less on time and within budget.
Incidentally, the reason why chip companies are worth so much more than IP companies is that the cost and risk of making chips is much larger. IP and chip companies are both fabless, if the costs and risks were about the same, then I don't see why profits wouldn't be about the same.
Now it could be that in this instance, marketability, schedule and budget weren't a particularly big deal, and maybe the performance is so bad that this in itself made a lot of problems disappear. But I think it's likely that someone still sweated quite some to make it work. (TFA claims they were the first to implement this CPU in silicon, BTW - again, could be easy enough if they didn't care about performance at all, or if Imagination did all the work on the synthesis scripts and the backend or held their hand, but if they wanted high performance and had to optimize synthesis and placement themselves, that's serious work. TSMC won't do it for you, either - they want a GDS-II file, and I don't think they outsourced the actual chip design.)
Don't ask me, it was mostly luck in my case. In general I think in chips even more than elsewhere you want to work at a small place to get big responsibilities quickly, and from that angle, right now doesn't look like a great time to enter the industry, since FinFET mask costs are 10x what they used to be in bulk CMOS and so the expected payout needed to justify risking the capital went up a lot, so less projects starting small. Maybe if node shrinks stop and mask costs go back down and people will start making plenty of specialized lower-volume chips since you won't be able to win just by shrinking high-volume architectures, it will be a good time to enter the industry again.
> "... since FinFET mask costs are 10x what they used to be in bulk CMOS"
Not true, it is closer to 2 to 3x, and it is (slowly) getting cheaper. While it will take a long time (~3 years) for 14/16nm FinFET processes to reach price parity with what 28nm is now, it is dropping in price faster than when the 28nm generation came out due to the massive volumes of Apple, NVIDIA, etc.
It is looking like the 28nm generation will be a mainstay node, with continued investments by the major pure play fabs to keep bringing costs lower.
>> It is looking like the 28nm generation will be a mainstay node, with continued investments by the major pure play fabs to keep bringing costs lower.
Is that because it's essentially the last planar node? IIRC 20nm kinda sucked for both planar and FinFET so 28 is the last planar and 14/16 is looking like a long term node as well. Is that why you think 28 will be a mainstay?
I'm seeing 28,14 and 7 as pretty much stable and widespread over the next 10 years, with 14 and 7 being significant for cost/perf and cost/density reasons.
like yosefk I sort of fell into it, worked for a company architecting stuff in pals/fpgas, it came time to build chips, someone else laid gates and I did the high level stuff, next time around it was easier for me to do it in verilog - after that I changed companies and build a bunch of SoCs with a larger team working as a logic designer.
After a decade or so I actually made a concious decision to stop building chips, once the novelty wore off I found I was doing a month's creative work a year and 11 months of timing and DV. As a systems software hack I'd get somthing woprking today, and something else tomorrow - much more of a sense of accomplishment - these days I do a bit of hardware and a bit of software - mostly embedded systems - I definitely enjoy it more
Erm... A shitton of tools. You roughly write and validate an HLL description, translate it to gates or more generally/correctly library cells and then place them and route the connecting wires. GDS-II has everything at an exact place, from that they make wafer masks. But each stage is many tools and it's not fully independent considerations.
Or you can use Chuck Moore's famous 500 lines of Forth to produce a chip for 180 nm that can't access DRAM and go on about everyone doing it wrong.
It's OK with the Russians. The performance is good enough.They probably care more about the verification against security issues, and could do interesting stuff there, but we surely won't hear about that.
Intel has two architecture teams, one in Israel and the other in Oregon. They also have fabs all over, with their big 14nm ones being in Oregon (D1X, D1D, D1C) and Arizona (Fab 12, 32 and 42).
Altogether, they have more fabs in the US than outside (7 vs 3).
I know was just still making a point that you can buy an Intel CPU today that was designed in Israel, manufactured in Ireland (Fab 24) and the packaged somewhere else and it's still "American".
