It VHDL as implemented at the time was broken, at least as of 2010. [0] VHDL 2008 support would have definitely had a positive impact on the VHDL source code (making it smaller and more comprehensible). There were so many 2008 features I wished to use but simply couldn't. With the slow pace that FPGA toolchains progress, I'd imagine the situation isn't vastly better today.
Luckily I read [1] and realized that VHDL can be written in a better way, even with old toolchains. This 2proc style is so much easier to debug than typical RTL syle. It was unfortunate that the 2010 era Quartus II toolchain did not optimize my behavioral code well. The CPU caches were the worst offenders, which isn't too surprising. Tons of enormous, almost certainly inefficient, muxes really pushed the LE limits on the FPGA and my patience during the very long synthesis time.
