Being a little pedantic, but you could use verilog to write a high level model as you describe. The language certainly doesn't restrict you to its synthesizable subset.
That being said, it's generally easier and cheaper (good verilog implementations aren't free) to use a general purpose language for what your describe.
That being said, it's generally easier and cheaper (good verilog implementations aren't free) to use a general purpose language for what your describe.