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Current Skylake Xeons don't have AVX-512 either. For example no AVX-512 in this Skylake Xeon: http://ark.intel.com/products/93354/Intel-Xeon-Processor-E3-...

I know about bandwidth issues, but you can also use big vector sizes to mitigate, more opportunities for simple schemes for realtime (de)compression of data. (Usually called packing/unpacking).

But where you can work around bandwidth issues, you can get up to twice as much work done.

I've also been looking for such a chip to test my code. Of course it's possible to use SDE. https://software.intel.com/en-us/articles/intel-software-dev...




Yeah the E3 Xeons won't have it, they're basically desktop chips dressed up. The E5s are supposed to have it though.




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