There are many Linux-capable CPU architectures in use today, including MIPS, x86, Power, ARC and others.
The world is moving towards an ISA-neutral, heterogeneous computing environment. If you look at an SoC today, it is very likely that it uses a combination of CPUs, including ARM, MIPS, ARC etc.
Furthermore, writing ARM code in GNU Assembler is a fairly unpleasant experience, while writing MIPS code in GNU Assembler is literally an into to Computer Science course.
Bingo, these are the same toolbags that were crowing about letting students see their magic sauce Verilog, which was license encumbered and definitely not as good as other fully open architectures out there.
Can you please define "not as good"? I'm trying to understand if you're referring to the quality of the hardware or the software ecosystem - or both.
MIPSfpga is a product for universities and academic institutions. There are a number of advantages of MIPSfpga over OpenRISC and RISC-V including:
1. The MIPS architecture is better supported by university text books. It is used as an example of a RISC architecture and an example of a CPU microarchitectural implementation in Patterson & Hennessy and in Harris & Harris
2. MIPSfpga shares Verilog source code with MIPS microAptiv UP - a commercial core that has many licensees including Microchip Technology and Samsung. The university professors have an interest to teach students about a CPU widely used by the industry, not a subset of an architecture, an old implementation of the architecture or a CPU core created only for academic purposes and not deployed by semiconductor companies.
3. The MIPS architecture is backed by a significant software ecosystem that includes a dozen of commercial RTOSes, official Linux support, compilers and debuggers, open source software, etc.
The point of MIPSfpga is not to deliver the solution optimized for a specific line of Xilinx FPGAs (like MicroBlaze) but to teach students general design practices, applicable to both FPGAs and ASICs. The code in MIPSfpga is not FPGA-specific. It uses Xilinx and Altera macros for memory in caches, but generally this is the same code used to make an ASIC.
The main idea of using MIPSfpga is that the students can play with the CPU core, create multicore systems, modify caches, etc. If they invent something useful, they can attract venture investment, buy a commercial license for MIPS microAptiv UP or MIPS M5150 and create their own ASIC design company.
What student capable of creating licensable IP would be swayed by the arguments listed for using a license encumbered architecture? None (or, precisely zero).
You can take those two books and apply the basics to Risc-V, develop the same IP, and pay zero - and it's already being used in ASICs as well. In fact it's better if you've never been polluted by seeing the license encumbered works, to prevent any claims about originality.
You missed SPIM as well! Despite being a bit long in the tooth, SPIM makes it really easy for students to step through MIPS assembly and get a good feel for how registers are mutated by the different instructions, etc.
I taught an architecture class using Patterson & Hennessy, and I wish I'd known about MIPSfpga at the time (maybe it didn't exist, it was a while ago). That would have definitely been helpful for the more eager students to dig deeper into how all this stuff works.
yep, imgtec has been trying to make MIPS happen for a while, presumably as a hedge against ARM. Not that MIPS is bad or anything (the bunny in Super Mario 64 was named MIPS after the CPU in the N64!) but there's no particular reason to choose MIPS if all you're doing is some tiny control loop or measuring some sensor every so often.
