On: John Mashey on RISC/CISC

[Scaevolus]

For context, here's the thread from 1991: https://groups.google.com/d/msg/comp.arch/rYgGszm_dGk/z7p0or...

One interesting comment:

    Hey, you left out the Acorn Risc Machine.  Not a big name in the
    workstation market, but I understand that they sell a good number of
    them, and the instruction set is "interesting" (a bit-twiddler/
    superoptimizer's wet dream, if you ask me, but probably "risc" by many
    definitions of the term).  VTI sells this chip in the US, they should
    be able to give you a spec if you want it.

I wonder what a modern table would look like. There's been a fair amount of turnover in RISC, now largely dominated by ARM, with MIPS and PowerPC also contenders, and CISC is still dominated by x86.

[kps → Scaevolus]

  > and the instruction set is "interesting" (a bit-twiddler/
  > superoptimizer's wet dream, if you ask me

All fallen by the wayside in Thumb and ARM64, now.

  > but probably "risc" by many definitions of the term

What ARM lacked in academic purity it made up in pragmatic simplicity of implementation. You could look at the instruction set and practically see the gates.

[renox → kps]

> What ARM lacked in academic purity it made up in pragmatic simplicity of implementation

'pragmatic simplicity of implementation'? Mmm, what about LDM/STM (load/store multiple registers)?

Of course they dropped this with the ARMv8 (64bit) ISA..

I wonder if they are still interesting differences between the ARMv8 and the MIPS ISA? From my (uninformed) POV they look very similar..