That is not quite the same thing. Andy's NVMe patches allow drive itself to go into deeper power-saving states, while discussion above was about power-management of SATA controller which is part of PCH (earlier known as northbridge), which in turn, on last 3 generations of Intel CPUs is integrated into the same die as CPU itself.
Unpleasant side-effect of SATA (or NVMe) controller being integrated onto the CPU die is that it now shares a power domain with the rest of the chip (i.e. PM being present or absent on SATA controller affects allowed set of C-states for the whole package). In other words, as long as SATA controller don't go into deep sleep (i.e. never - without power management enabled), whole CPU+PCH package would not go to deeper C-state. Thus, lack of PM in storage controller has disproportionately high effect on the total system power consumption.
Unpleasant side-effect of SATA (or NVMe) controller being integrated onto the CPU die is that it now shares a power domain with the rest of the chip (i.e. PM being present or absent on SATA controller affects allowed set of C-states for the whole package). In other words, as long as SATA controller don't go into deep sleep (i.e. never - without power management enabled), whole CPU+PCH package would not go to deeper C-state. Thus, lack of PM in storage controller has disproportionately high effect on the total system power consumption.